366 search results - page 29 / 74 » Circuit optimization using statistical static timing analysi... |
ASPDAC
2008
ACM
15 years 1 months ago
2008
ACM
The timing models used in current Static Timing Analysis tools use gate delays only for single input switching events. It is well known that the temporal proximity of signals arriv...
IEEEPACT
1999
IEEE
15 years 4 months ago
1999
IEEE
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
125
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CASES
2008
ACM
15 years 1 months ago
2008
ACM
We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for s...
ICSE
2009
IEEE-ACM
16 years 17 days ago
2009
IEEE-ACM
A variety of compilers, static analyses, and testing frameworks rely heavily on path frequency information. Uses for such information range from optimizing transformations to bug ...
110
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TASE
2007
IEEE
15 years 6 months ago
2007
IEEE
Software has been under scrutiny by the verification community from various angles in the recent past. There are two major algorithmic approaches to ensure the correctness of and...