253 search results - page 35 / 51 » Circuit partitions and |
DAC
1996
ACM
15 years 2 months ago
1996
ACM
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
79
Voted
TON
1998
14 years 9 months ago
1998
— This paper investigates in detail the blocking and nonblocking behavior of multirate Clos switching networks at the connection/virtual connection level. The results are applica...
106
Voted
ISPD
2007
ACM
14 years 11 months ago
2007
ACM
In this paper, we derive the X-half-perimeter wirelength (XHPWL) model for X-architecture placement and explore the effects of three different wire models on X-architecture plac...
65
Voted
VTS
2002
IEEE
15 years 3 months ago
2002
IEEE
Run-length codes and their variants have recently been shown to be very effective for compressing system-on-achip (SOC) test data. In this paper, we analyze the Golomb code, the c...
90
Voted
ITC
1999
IEEE
15 years 2 months ago
1999
IEEE
A high-level built-in self-test (BIST) synthesis involves several tasks such as system register assignment, interconnection assignment, and BIST register assignment. Existing high...