191 search results - page 6 / 39 » Clock Distribution Design in VLSI Circuits. An Overview |
DFT
2006
IEEE
15 years 1 months ago
2006
IEEE
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
IPPS
2002
IEEE
15 years 2 months ago
2002
IEEE
Hydra is a computer hardware description language that integrates several kinds of software tool (simulation, netlist generation and timing analysis) within a single circuit speci...
DATE
1998
IEEE
15 years 1 months ago
1998
IEEE
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
Abstract-- Nanometer VLSI systems demand robust clock distribution network design for increased process and operating condition variabilities. In this paper, we propose minimum clo...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—In modern sub-micron design, achieving low-skew clock distributions is facing challenges for high-performance circuits. Symmetric global clock distribution and clock tree synthe...