191 search results - page 8 / 39 » Clock Distribution Design in VLSI Circuits. An Overview |
GLVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
DAC
1996
ACM
15 years 1 months ago
1996
ACM
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...
68
Voted
ISLPED
2003
ACM
15 years 2 months ago
2003
ACM
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes would be promising approaches for futu...
GLVLSI
2005
IEEE
15 years 3 months ago
2005
IEEE
Energy recovery clocking results in significant energy savings in clock distribution networks as compared to conventional squarewave clocking. However, since energy recovery clock...
ISVLSI
2007
IEEE
15 years 3 months ago
2007
IEEE
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...