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ASPDAC
1999
ACM
105views Hardware» more  ASPDAC 1999»
15 years 1 months ago
Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion
Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani
DAC
2005
ACM
15 years 10 months ago
Race-condition-aware clock skew scheduling
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...
Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu