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ASPDAC
1999
ACM

105views Hardware» more ASPDAC 1999»

Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion

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Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion

Download www.lab.ss.titech.ac.jp

Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani

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Added	02 Aug 2010
Updated	02 Aug 2010
Type	Conference
Year	1999
Where	ASPDAC
Authors	Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani

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