205 search results - page 17 / 41 » Clock gating architectures for FPGA power reduction |
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimization...
111
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ANCS
2008
ACM
14 years 11 months ago
2008
ACM
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
ISLPED
2010
ACM
14 years 9 months ago
2010
ACM
Structured ASICs provide an exciting middle ground between FPGA and ASIC design methodologies. Compared to ASIC, structured ASIC based designs require lower non recurring engineer...
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
A negative effect of ever-shrinking supply and threshold voltages is the larger percentage of total power consumption that comes from leakage current. Several techniques have been...
74
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FTEDA
2007
14 years 9 months ago
2007
Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their archite...