96 search results - page 19 / 20 » Clock-Aware Placement for FPGAs |
FPL
2003
Springer
13 years 11 months ago
2003
Springer
Local search methods such as WSAT have proven to be successful for solving SAT problems. In this paper, we propose two host-FPGA (Field Programmable Gate Array) co-implementations,...
DAC
2006
ACM
14 years 7 months ago
2006
ACM
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
FPGA
2004
ACM
13 years 11 months ago
2004
ACM
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
FPGA
2009
ACM
14 years 1 months ago
2009
ACM
Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the inte...
FCCM
2005
IEEE
13 years 12 months ago
2005
IEEE
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...