169 search results - page 2 / 34 » Co-Scheduling Hardware and Software Pipelines |
102
Voted
EGH
2011
Springer
13 years 9 months ago
2011
Springer
In this paper, we implement an efficient, completely software-based graphics pipeline on a GPU. Unlike previous approaches, we obey ordering constraints imposed by current graphi...
72
Voted
HCI
2009
14 years 7 months ago
2009
This paper presents the TACTUS Multi-Touch Research Testbed, a hardware and software system for enabling research in multi-touch interaction. A detailed discussion is provided on h...
ISCA
1989
IEEE
15 years 1 months ago
1989
IEEE
Pipelining has become a common technique to increase throughput of the instruction fetch, instruction decode, and instruction execution portions of modern computers. Branch instru...
69
Voted
ISSS
1997
IEEE
15 years 1 months ago
1997
IEEE
Given a hardware/software partitioned specification and an allocation (number and type) of processors, we present an algorithm to (1) map each of the software behaviors (or tasks...
DAC
1996
ACM
15 years 1 months ago
1996
ACM
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...