Sciweavers

1225 search results - page 219 / 245
» Code Compression for Embedded Systems
Sort
View
CODES
2007
IEEE
15 years 4 months ago
Thread warping: a framework for dynamic synthesis of thread accelerators
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
Greg Stitt, Frank Vahid
CODES
2007
IEEE
15 years 4 months ago
Event-based re-training of statistical contention models for heterogeneous multiprocessors
Embedded single-chip heterogeneous multiprocessor (SCHM) systems experience frequent system events such as task preemption, power-saving voltage/frequency scaling, or arrival of n...
Alex Bobrek, JoAnn M. Paul, Donald E. Thomas
AAECC
2003
Springer
139views Algorithms» more  AAECC 2003»
15 years 2 months ago
Fighting Two Pirates
A pirate is a person who buys a legal copy of a copyrighted work and who reproduces it to sell illegal copies. Artists and authors are worried as they do not get the income which i...
Hans Georg Schaathun
CODES
2005
IEEE
15 years 3 months ago
Improving superword level parallelism support in modern compilers
Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology...
Christian Tenllado, Luis Piñuel, Manuel Pri...
CODES
2009
IEEE
15 years 2 months ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...