Sciweavers

966 search results - page 9 / 194
» Code Generation for Embedded Processors
Sort
View
SAC
2006
ACM
15 years 3 months ago
Implementing an embedded GPU language by combining translation and generation
Dynamic languages typically allow programs to be written y high level of abstraction. But their dynamic nature makes it very hard to compile such languages, meaning that a price h...
Calle Lejdfors, Lennart Ohlsson
CASES
2007
ACM
15 years 1 months ago
Fragment cache management for dynamic binary translators in embedded systems with scratchpad
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...
José Baiocchi, Bruce R. Childers, Jack W. D...
IPPS
1998
IEEE
15 years 1 months ago
PACE: Processor Architectures for Circuit Emulation
We describe a family of reconfigurable parallel architectures for logic emulation. They are supposed to be applicable like conventional FPGAs, while covering a larger range of circ...
Reiner Kolla, Oliver Springauf
CODES
2008
IEEE
15 years 4 months ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava