21 search results - page 4 / 5 » Coherence Communication Prediction in Shared-Memory Multipro... |
ISCA
1998
IEEE
15 years 2 months ago
1998
IEEE
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
ISCA
2000
IEEE
15 years 2 months ago
2000
IEEE
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
88
Voted
CODES
2009
IEEE
15 years 3 months ago
2009
IEEE
In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Here, we target at heterogeneous MPSoCs with a network-on-chip (NoC). Existing har...
117
Voted
PVM
1997
Springer
15 years 2 months ago
1997
Springer
The extremely low latencies and high bandwidth results achievable with the Scalable Coherent Interface SCI at lowest level encourages its integration into existing Message Passin...
75
Voted
ISPASS
2005
IEEE
15 years 3 months ago
2005
IEEE
Communication misses--those serviced by dirty data in remote caches--are a pressing performance limiter in shared-memory multiprocessors. Recent research has indicated that tempor...