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» Combining optimizations in automated low power design
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GLVLSI
2010
IEEE
310views VLSI» more  GLVLSI 2010»
15 years 2 months ago
Graphene tunneling FET and its applications in low-power circuit design
Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...
Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Moh...
EMSOFT
2005
Springer
15 years 3 months ago
A sink-n-hoist framework for leakage power reduction
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts have tried to integrate architecture...
Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee
ETT
2007
99views Education» more  ETT 2007»
14 years 9 months ago
On the design of rate-compatible serially concatenated convolutional codes
A powerful class of rate-compatible serially concatenated convolutional codes (SCCCs) has been proposed based on minimizing analytical upper bounds on the error probability in the ...
Alexandre Graell i Amat, Fredrik Brännstr&oum...
ICIP
2003
IEEE
15 years 11 months ago
Design of Q-shift complex wavelets for image processing using frequency domain energy minimization
This paper proposes a new method of designing finitesupport wavelet filters, based on minimization of energy in key parts of the frequency domain. In particular this technique is ...
Nick G. Kingsbury
ICCD
1996
IEEE
104views Hardware» more  ICCD 1996»
15 years 2 months ago
Latch Redundancy Removal Without Global Reset
For circuits where there may be latches with no reset line, we show how to replace some of them with combinational logic. All previous work in sequential optimization by latch rem...
Shaz Qadeer, Robert K. Brayton, Vigyan Singhal