37 search results - page 7 / 8 » Compact FPGA implementations of QUAD |
GLVLSI
2007
IEEE
13 years 10 months ago
2007
IEEE
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
ERSA
2007
13 years 7 months ago
2007
The emergence of high-density reconfigurable hardware devices gives scientists and engineers an option to accelerating their numerical computing applications on low-cost but power...
DFT
2006
IEEE
14 years 13 days ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
ARITH
2009
IEEE
14 years 1 months ago
2009
IEEE
—The real Logarithmic Number System (LNS) allows fast and inexpensive multiplication and division but more expensive addition and subtraction as precision increases. Recent advan...
FPL
2010
Springer
13 years 4 months ago
2010
Springer
We demonstrate how Field Programmable Gate Arrays (FPGAs) may be used to address the computing challenges associated with assembling genome sequences from recent ultra-high-through...