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CGO
2004
IEEE
15 years 3 months ago
Specialized Dynamic Optimizations for High-Performance Energy-Efficient Microarchitecture
We study several major characteristics of dynamic optimization within the PARROT power-aware, trace-cachebased microarchitectural framework. We investigate the benefit of providin...
Yoav Almog, Roni Rosner, Naftali Schwartz, Ari Sch...
AUSDM
2008
Springer
238views Data Mining» more  AUSDM 2008»
15 years 1 months ago
Graphics Hardware based Efficient and Scalable Fuzzy C-Means Clustering
The exceptional growth of graphics hardware in programmability and data processing speed in the past few years has fuelled extensive research in using it for general purpose compu...
S. A. Arul Shalom, Manoranjan Dash, Minh Tue
MTV
2007
IEEE
121views Hardware» more  MTV 2007»
15 years 6 months ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco
EMSOFT
2005
Springer
15 years 5 months ago
Optimizing inter-processor data locality on embedded chip multiprocessors
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
Guilin Chen, Mahmut T. Kandemir
ISCA
2010
IEEE
163views Hardware» more  ISCA 2010»
15 years 4 months ago
WiDGET: Wisconsin decoupled grid execution tiles
The recent paradigm shift to multi-core systems results in high system throughput within a specified power budget. However, future systems still require good single thread perfor...
Yasuko Watanabe, John D. Davis, David A. Wood