5122 search results - page 269 / 1025 » Comparing Consequence Relations |
117
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ISCA
1997
IEEE
15 years 9 months ago
1997
IEEE
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...
135
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ITC
1997
IEEE
15 years 9 months ago
1997
IEEE
Testing embedded cores is a challenge because access to core I/Os is limited. The user-defined logic (ZJDL) surrounding the core may restrict the set of test vectors that can be a...
129
Voted
VLSID
1996
IEEE
15 years 9 months ago
1996
IEEE
The paper presents QCAMP, a cube-based algorithm for minimization of single Boolean functions. The algorithm does not generate all the prime cubes, nor does it require the Off-set...
134
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ICCAD
1994
IEEE
15 years 9 months ago
1994
IEEE
- This paper addresses the problem of true delay estimation during high level design. The existing delay estimation techniques either estimate the topological delay of the circuit ...
139
Voted
IWMM
2010
Springer
15 years 9 months ago
2010
Springer
Concurrent and incremental collectors require barriers to ensure correct synchronisation between mutator and collector. The overheads imposed by particular barriers on particular ...