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DATE
2003
IEEE
127views Hardware» more  DATE 2003»
16 years 3 days ago
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
16 years 3 days ago
Area Fill Generation With Inherent Data Volume Reduction
Control of variability and performance in the back end of the VLSI manufacturing line has become extremely difficult with the introduction of new materials such as copper and low...
Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexande...
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
16 years 3 days ago
A Novel Metric for Interconnect Architecture Performance
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Mud...
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ICAT
2003
IEEE
16 years 3 days ago
Head Motion Prediction in Augmented Reality Systems Using Monte Carlo Particle Filters
A basic problem with Augmented Reality systems using Head-Mounted Displays (HMDs) is the perceived latency or lag. This delay corresponds to the elapsed time between the moment wh...
Fakhreddine Ababsa, Jean-Yves Didier, Malik Mallem...
ICDM
2003
IEEE
100views Data Mining» more  ICDM 2003»
16 years 3 days ago
Tractable Group Detection on Large Link Data Sets
Discovering underlying structure from co-occurrence data is an important task in a variety of fields, including: insurance, intelligence, criminal investigation, epidemiology, hu...
Jeremy Kubica, Andrew W. Moore, Jeff G. Schneider