In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
Control of variability and performance in the back end of the VLSI manufacturing line has become extremely difficult with the introduction of new materials such as copper and low...
Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexande...
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Mud...
A basic problem with Augmented Reality systems using Head-Mounted Displays (HMDs) is the perceived latency or lag. This delay corresponds to the elapsed time between the moment wh...
Fakhreddine Ababsa, Jean-Yves Didier, Malik Mallem...
Discovering underlying structure from co-occurrence data is an important task in a variety of fields, including: insurance, intelligence, criminal investigation, epidemiology, hu...