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» Comparing memory systems for chip multiprocessors
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102
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RSP
2007
IEEE
143views Control Systems» more  RSP 2007»
15 years 3 months ago
Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs
Multiprocessor Systems-on-Chip (MPSoCs) is a trend in VLSI design, since they minimize the “design crisis” (gap between silicon technology and actual SoC design capacity) and ...
Ewerson Carvalho, Ney Calazans, Fernando Moraes
88
Voted
GECCO
2003
Springer
142views Optimization» more  GECCO 2003»
15 years 2 months ago
Revisiting Elitism in Ant Colony Optimization
Ant Colony Optimization (ACO) has been applied successfully in solving the Traveling Salesman Problem. Marco Dorigo et al. used Ant System (AS) to explore the Symmetric Traveling S...
Tony White, Simon Kaegi, Terri Oda
88
Voted
IPPS
2007
IEEE
15 years 3 months ago
Virtual Execution Environments: Support and Tools
In today’s dynamic computing environments, the available resources and even underlying computation engine can change during the execution of a program. Additionally, current tre...
Apala Guha, Jason Hiser, Naveen Kumar, Jing Yang, ...
ICPP
2005
IEEE
15 years 3 months ago
Exploring Processor Design Options for Java-Based Middleware
Java-based middleware is a rapidly growing workload for high-end server processors, particularly Chip Multiprocessors (CMP). To help architects design future microprocessors to ru...
Martin Karlsson, Erik Hagersten, Kevin E. Moore, D...
77
Voted
SAMOS
2004
Springer
15 years 2 months ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope