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CGO
2004
IEEE
15 years 1 months ago
VHC: Quickly Building an Optimizer for Complex Embedded Architectures
To meet the high demand for powerful embedded processors, VLIW architectures are increasingly complex (e.g., multiple clusters), and moreover, they now run increasingly sophistica...
Michael Dupré, Nathalie Drach, Olivier Tema...
ASPDAC
2006
ACM
143views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Constraint-driven bus matrix synthesis for MPSoC
– Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based com...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
RSP
2005
IEEE
155views Control Systems» more  RSP 2005»
15 years 3 months ago
Optimization Techniques for ADL-Driven RTL Processor Synthesis
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
Oliver Schliebusch, Anupam Chattopadhyay, Ernst Ma...
ASPDAC
2008
ACM
135views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Temperature-aware MPSoC scheduling for reducing hot spots and gradients
Thermal hot spots and temperature gradients on the die need to be minimized to manufacture reliable systems while meeting energy and performance constraints. In this work, we solve...
Ayse Kivilcim Coskun, Tajana Simunic Rosing, Keith...
ICCAD
2007
IEEE
116views Hardware» more  ICCAD 2007»
15 years 6 months ago
Device and architecture concurrent optimization for FPGA transient soft error rate
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...
Yan Lin, Lei He