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» Comparing the Optimal Performance of Parallel Architectures
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165
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CODES
2004
IEEE
15 years 7 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
165
Voted
DMIN
2006
126views Data Mining» more  DMIN 2006»
15 years 5 months ago
Comparison and Analysis of Mutation-based Evolutionary Algorithms for ANN Parameters Optimization
Mutation-based Evolutionary Algorithms, also known as Evolutionary Programming (EP) are commonly applied to Artificial Neural Networks (ANN) parameters optimization. This paper pre...
Kristina Davoian, Alexander Reichel, Wolfram-Manfr...
125
Voted
EDBT
2008
ACM
161views Database» more  EDBT 2008»
16 years 3 months ago
Load distribution of analytical query workloads for database cluster architectures
Enterprises may have multiple database systems spread across the organization for redundancy or for serving different applications. In such systems, query workloads can be distrib...
Thomas Phan, Wen-Syan Li
110
Voted
EUROPAR
2010
Springer
15 years 4 months ago
Non-clairvoyant Scheduling of Multiple Bag-of-Tasks Applications
The bag-of-tasks application model, albeit simple, arises in many application domains and has received a lot of attention in the scheduling literature. Previous works propose eithe...
Henri Casanova, Matthieu Gallet, Fréd&eacut...
127
Voted
ASPDAC
2006
ACM
143views Hardware» more  ASPDAC 2006»
15 years 9 months ago
Constraint-driven bus matrix synthesis for MPSoC
– Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based com...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...