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» Comparing the Optimal Performance of Parallel Architectures
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138
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HPCA
2008
IEEE
15 years 10 months ago
Speculative instruction validation for performance-reliability trade-off
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
146
Voted
CLUSTER
2002
IEEE
15 years 3 months ago
File and Object Replication in Data Grids
Data replication is a key issue in a Data Grid and can be managed in different ways and at different levels of granularity: for example, at the file level or object level. In the ...
Heinz Stockinger, Asad Samar, Koen Holtman, Willia...
210
Voted
ARC
2012
Springer
317views Hardware» more  ARC 2012»
13 years 11 months ago
A High Throughput FPGA-Based Implementation of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem
Iterative numerical algorithms with high memory bandwidth requirements but medium-size data sets (matrix size ∼ a few 100s) are highly appropriate for FPGA acceleration. This pap...
Abid Rafique, Nachiket Kapre, George A. Constantin...
121
Voted
TVCG
2008
112views more  TVCG 2008»
15 years 3 months ago
Chromium Renderserver: Scalable and Open Remote Rendering Infrastructure
Abstract-Chromium Renderserver (CRRS) is software infrastructure that provides the ability for one or more users to run and view image output from unmodified, interactive OpenGL an...
Brian E. Paul, Sean Ahern, E. Wes Bethel, Eric Bru...
117
Voted
ACSAC
2000
IEEE
15 years 8 months ago
The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip
The performance of RSA hardware is primarily determined by an efficient implementation of the long integer modular arithmetic and the ability to utilize the Chinese Remainder The...
Johann Großschädl