1461 search results - page 193 / 293 » Comparing the Optimal Performance of Parallel Architectures |
108
Voted
TASLP
2008
15 years 3 months ago
2008
The parallel phone recognition followed by language model (PPRLM) architecture represents one of the state-of-the-art spoken language identification systems. A PPRLM system compris...
125
Voted
DAC
2006
ACM
16 years 4 months ago
2006
ACM
Deploying multiple supply voltages (multi-Vdds) on one chip is an important technique to reduce dynamic power consumption. In this work we present an optimality study for resource...
170
Voted
VEE
2005
ACM
15 years 9 months ago
2005
ACM
We present an optimized implementation of the linear scan register allocation algorithm for Sun Microsystems’ Java HotSpotTM client compiler. Linear scan register allocation is ...
144
Voted
HPCA
2007
IEEE
16 years 4 months ago
2007
IEEE
This paper evaluates the suitability of the MapReduce model for multi-core and multi-processor systems. MapReduce was created by Google for application development on data-centers...
120
Voted
IPPS
2007
IEEE
15 years 10 months ago
2007
IEEE
Multi-core processors are a shift of paradigm in computer architecture that promises a dramatic increase in performance. But multi-core processors also bring an unprecedented leve...