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» Comparing the Optimal Performance of Parallel Architectures
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ASPLOS
2011
ACM
14 years 3 months ago
Inter-core prefetching for multicore processors using migrating helper threads
Multicore processors have become ubiquitous in today’s systems, but exploiting the parallelism they offer remains difficult, especially for legacy application and applications ...
Md Kamruzzaman, Steven Swanson, Dean M. Tullsen
86
Voted
DAC
2009
ACM
16 years 26 days ago
Event-driven gate-level simulation with GP-GPUs
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely ? from high-level descriptions down to gate-level ones ?...
Debapriya Chatterjee, Andrew DeOrio, Valeria Berta...
IWCMC
2006
ACM
15 years 5 months ago
Budgeting power: packet duplication and bit error rate reduction in wireless ad-hoc networks
In this paper we present and evaluate a new technique to lower packet-level error rates of application layer connections in wireless ad-hoc networks. In our scheme, data packets s...
Ghassen Ben Brahim, Bilal Khan
ACMACE
2006
ACM
15 years 5 months ago
Wireless home entertainment center: reducing last hop delays for real-time applications
Future digital entertainment services available to home users will share several characteristics: i) they will be deployed and delivered through the Internet, ii) a single media c...
Claudio E. Palazzi, Giovanni Pau, Marco Roccetti, ...
DDECS
2007
IEEE
102views Hardware» more  DDECS 2007»
15 years 6 months ago
IP Integration Overhead Analysis in System-on-Chip Video Encoder
—Current system-on-chip implementations integrate IP blocks from different vendors. Typical problems are incompatibility and integration overheads. This paper presents a case stu...
Antti Rasmus, Ari Kulmala, Erno Salminen, Timo D. ...