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» Comparing the Optimal Performance of Parallel Architectures
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DAC
2006
ACM
16 years 2 months ago
Optimal simultaneous mapping and clustering for FPGA delay optimization
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
Joey Y. Lin, Deming Chen, Jason Cong
IEEEPACT
2005
IEEE
15 years 7 months ago
Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor
While general-purpose processors have only recently employed chip multiprocessor (CMP) architectures, network processors (NPs) have used heterogeneous multi-core architectures sin...
Ben Wun, Jeremy Buhler, Patrick Crowley
IPPS
2007
IEEE
15 years 8 months ago
Advanced Shortest Paths Algorithms on a Massively-Multithreaded Architecture
We present a study of multithreaded implementations of Thorup’s algorithm for solving the Single Source Shortest Path (SSSP) problem for undirected graphs. Our implementations l...
Joseph R. Crobak, Jonathan W. Berry, Kamesh Maddur...
EUROMICRO
1998
IEEE
15 years 6 months ago
Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems
The paper presents an approach to process scheduling for embedded systems. Target architectures consist of several processors and ASICs connected by shared busses. We have develop...
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa...
CORR
2010
Springer
144views Education» more  CORR 2010»
15 years 1 months ago
A Parallel Framework for Multilayer Perceptron for Human Face Recognition
Artificial neural networks have already shown their success in face recognition and similar complex pattern recognition tasks. However, a major disadvantage of the technique is th...
Mrinal Kanti Bhowmik, Debotosh Bhattacharjee, Mita...