1461 search results - page 82 / 293 » Comparing the Optimal Performance of Parallel Architectures |
ASAP
2007
IEEE
15 years 8 months ago
2007
IEEE
With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip and multicore architect...
102
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ICMCS
2007
IEEE
15 years 8 months ago
2007
IEEE
This paper introduces the software framework MMER Lab which allows an effective assembly of modular signal processing systems optimized for memory efficiency and performance. Our...
88
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SIPS
2007
IEEE
15 years 8 months ago
2007
IEEE
In this paper, the Time-Division Multiplexing (TDM) architecture for the Hybrid Filter Bank (HFB) A/D Converters (ADCs) is studied in the time domain. Giving a brief survey on the...
115
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IPPS
2009
IEEE
15 years 8 months ago
2009
IEEE
Many image and signal processing kernels can be optimized for performance consuming a reasonable area by doing loops parallelization with extensive use of pipelining. This paper p...
122
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CLUSTER
2007
IEEE
15 years 8 months ago
2007
IEEE
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...