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SAINT
2008
IEEE
15 years 10 months ago
A Prototype of a Multi-core Wireless Sensor Node for Reducing Power Consumption
This paper presents initial experiment results toward realizing a multi-core CPU for wireless sensor nodes. The multi-core CPU reduces power consumption with enabling users to eas...
Sotaro Ohara, Makoto Suzuki, Shunsuke Saruwatari, ...
ISCAS
2006
IEEE
113views Hardware» more  ISCAS 2006»
15 years 10 months ago
Low power state-parallel relaxed adaptive Viterbi decoder design and implementation
Abstract— In this paper, we present an algorithm/architecturelevel design solution for implementing state-parallel adaptive Viterbi decoders that, compared with their Viterbi cou...
Fei Sun, Tong Zhang
IWSOC
2005
IEEE
141views Hardware» more  IWSOC 2005»
15 years 9 months ago
Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital Circuits
This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to lowvoltage/low-power digital circuitry. The simulated power consumption of standard CMOS g...
Kenneth A. Townsend, James W. Haslett, Krzysztof I...
ISCAS
2003
IEEE
93views Hardware» more  ISCAS 2003»
15 years 9 months ago
A low power charge sharing ROM using dummy bit lines
This paper proposes a shared-capacitor charge-sharing ROM (SCCS-ROM). The SCCS-ROM reduces the swing voltage using the charge-sharing technique of the charge-sharing ROM (CSROM) [...
Byung-Do Yang, Lee-Sup Kim
DATE
2000
IEEE
89views Hardware» more  DATE 2000»
15 years 8 months ago
Architectural Power Optimization by Bus Splitting
– A split-bus architecture is proposed to improve the power dissipation for global data exchange among a set of modules. The resulting bus splitting problem is formulated and sol...
Cheng-Ta Hsieh, Massoud Pedram