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» Compiled hardware acceleration of Molecular Dynamics code
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87
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LCTRTS
2007
Springer
15 years 3 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
VLSISP
2008
173views more  VLSISP 2008»
14 years 9 months ago
Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors
Advanced bit manipulation operations are not efficiently supported by commodity word-oriented microprocessors. Programming tricks are typically devised to shorten the long sequence...
Yedidya Hilewitz, Ruby B. Lee
68
Voted
ASPLOS
2004
ACM
15 years 3 months ago
HIDE: an infrastructure for efficiently protecting information leakage on the address bus
+ XOM-based secure processor has recently been introduced as a mechanism to provide copy and tamper resistant execution. XOM provides support for encryption/decryption and integrit...
Xiaotong Zhuang, Tao Zhang, Santosh Pande
101
Voted
ISCA
2012
IEEE
208views Hardware» more  ISCA 2012»
12 years 12 months ago
Harmony: Collection and analysis of parallel block vectors
Efficient execution of well-parallelized applications is central to performance in the multicore era. Program analysis tools support the hardware and software sides of this effor...
Melanie Kambadur, Kui Tang, Martha A. Kim
80
Voted
IPPS
2006
IEEE
15 years 3 months ago
Analysis of checksum-based execution schemes for pipelined processors
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
Bernhard Fechner