Sciweavers

138 search results - page 15 / 28
» Compiled-code-based simulation with timing verification
Sort
View
DAC
1999
ACM
15 years 4 months ago
Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...
Lisa M. Guerra, Joachim Fitzner, Dipankar Talukdar...
ATVA
2008
Springer
159views Hardware» more  ATVA 2008»
15 years 1 months ago
Component-Based Design and Analysis of Embedded Systems with UPPAAL PORT
UPPAAL PORT is a new tool for component-based design and analysis of embedded systems. It operates on the hierarchically structured continuous time component modeling language Save...
John Håkansson, Jan Carlson, Aurelien Monot,...
FMCAD
2006
Springer
15 years 3 months ago
Design for Verification of the PCI-X Bus
The importance of re-usable Intellectual Properties (IPs) cores is increasing due to the growing complexity of today's system-on-chip and the need for rapid prototyping. In th...
Haja Moinudeen, Ali Habibi, Sofiène Tahar
DAC
2010
ACM
15 years 3 months ago
Scalable specification mining for verification and diagnosis
Effective system verification requires good specifications. The lack of sufficient specifications can lead to misses of critical bugs, design re-spins, and time-to-market slips. I...
Wenchao Li, Alessandro Forin, Sanjit A. Seshia
DATE
2003
IEEE
134views Hardware» more  DATE 2003»
15 years 5 months ago
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration
The design of high performance multimedia systems in a short time force us to use IP's blocks in many designs. However, their correct integration in a design implies more com...
Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Ri...