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157
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ISCA
1993
IEEE
125views Hardware» more  ISCA 1993»
15 years 7 months ago
Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5
er uses an abstract machine approach to compare the mechanisms of two parallel machines: the J-Machine and the CM-5. High-level parallel programs are translated by a single optimi...
Ellen Spertus, Seth Copen Goldstein, Klaus E. Scha...
125
Voted
ISCA
2010
IEEE
340views Hardware» more  ISCA 2010»
15 years 8 months ago
Necromancer: enhancing system throughput by animating dead cores
Aggressive technology scaling into the nanometer regime has led to a host of reliability challenges in the last several years. Unlike onchip caches, which can be efficiently prot...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
128
Voted
IPPS
2007
IEEE
15 years 10 months ago
The Next Generation Software Workshop - IPDPS'07
This workshop provides a forum for an overview, project presentations, and discussion of the research fostered and funded initially by the NSF Next Generation Software (NGS) Progr...
Frederica Darema
136
Voted
TSMC
2010
14 years 10 months ago
An Architecture for Adaptive Algorithmic Hybrids
We describe a cognitive architecture for creating more robust intelligent systems by executing hybrids of algorithms based on different computational formalisms. The architecture ...
Nicholas L. Cassimatis, Perrin G. Bignoli, Magdale...
140
Voted
LCTRTS
2004
Springer
15 years 9 months ago
Spinach: a liberty-based simulator for programmable network interface architectures
This paper presents Spinach, a new simulator toolset specifically designed to target programmable network interface architectures. Spinach models both system components that are ...
Paul Willmann, Michael Brogioli, Vijay S. Pai