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» Compiler Support for Reducing Leakage Energy Consumption
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EMSOFT
2004
Springer
15 years 2 months ago
Binary translation to improve energy efficiency through post-pass register re-allocation
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both hig...
Kun Zhang, Tao Zhang, Santosh Pande
ICCAD
2002
IEEE
157views Hardware» more  ICCAD 2002»
15 years 6 months ago
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power savings by DVS alone is becoming limi...
Steven M. Martin, Krisztián Flautner, Trevo...
ASPDAC
2008
ACM
97views Hardware» more  ASPDAC 2008»
14 years 11 months ago
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures
Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt
74
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DATE
2002
IEEE
104views Hardware» more  DATE 2002»
15 years 2 months ago
A Compiler-Based Approach for Improving Intra-Iteration Data Reuse
Intra-iteration data reuse occurs when multiple array references exhibit data reuse in a single loop iteration. An optimizing compiler can exploit this reuse by clustering (in the...
Mahmut T. Kandemir
CSREAESA
2007
14 years 11 months ago
The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems
- Several studies have shown that cache memories account for more than 40% of the total energy consumed in processor-based embedded systems. In microscale technology nodes, active ...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...