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» Compiler Support for Reducing Leakage Energy Consumption
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73
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GLVLSI
2009
IEEE
167views VLSI» more  GLVLSI 2009»
15 years 4 months ago
Dual-threshold pass-transistor logic design
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. ...
EUROCRYPT
2010
Springer
15 years 2 months ago
Protecting Circuits from Leakage: the Computationally-Bounded and Noisy Cases
Abstract. Physical computational devices leak side-channel information that may, and often does, reveal secret internal states. We present a general transformation that compiles an...
Sebastian Faust, Tal Rabin, Leonid Reyzin, Eran Tr...
IPCCC
2006
IEEE
15 years 3 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
74
Voted
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
15 years 10 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
DAC
2002
ACM
15 years 10 months ago
An energy saving strategy based on adaptive loop parallelization
In this paper, we evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using different number of processors if doing so is be...
Ismail Kadayif, Mahmut T. Kandemir, Mustafa Karak&...