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FPL
2009
Springer
154views Hardware» more  FPL 2009»
15 years 2 months ago
Compiler assisted runtime task scheduling on a reconfigurable computer
Multitasking reconfigurable computers with one or more reconfigurable processors are being used increasingly during the past few years. One of the major challenges in such systems...
Mojtaba Sabeghi, Vlad Mihai Sima, Koen Bertels
PLDI
1995
ACM
15 years 1 months ago
Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
Jack L. Lo, Susan J. Eggers
92
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CAMP
2005
IEEE
15 years 3 months ago
Development of a Bit-Level Compiler for Massively Parallel Vision Chips
Abstract— An image sensor in which each pixel has a processing element is called a vision chip. The vision chip can perform real-time visual processing at a high frame rate of 10...
Takashi Komuro, Shingo Kagami, Masatoshi Ishikawa,...
ENTCS
2007
108views more  ENTCS 2007»
14 years 9 months ago
Simulating and Compiling Code for the Sequential Quantum Random Access Machine
We present the SQRAM architecture for quantum computing, which is based on Knill’s QRAM model. We detail a suitable instruction set, which implements a universal set of quantum ...
Rajagopal Nagarajan, Nikolaos Papanikolaou, David ...
CLUSTER
2008
IEEE
15 years 4 months ago
Intelligent compilers
—The industry is now in agreement that the future of architecture design lies in multiple cores. As a consequence, all computer systems today, from embedded devices to petascale ...
John Cavazos