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RECONFIG
2009
IEEE
269views VLSI» more  RECONFIG 2009»
15 years 4 months ago
A 10 Gbps OTN Framer Implementation Targeting FPGA Devices
Abstract—Integrated circuits for very high-speed telecommunication protocols often use ASICs, due to their strict timing constraints. This scenario is changing, since modern FPGA...
Guilherme Guindani, Frederico Ferlini, Jeferson Ol...
85
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IPPS
2007
IEEE
15 years 4 months ago
Exploring a Multithreaded Methodology to Implement a Network Communication Protocol on the Cyclops-64 Multithreaded Architecture
The IBM Cyclops-64 (C64) chip employs a multithreaded architecture that integrates a large number of hardware thread units on a single chip. A cellular supercomputer is being deve...
Ge Gan, Ziang Hu, Juan del Cuvillo, Guang R. Gao
ARITH
1999
IEEE
15 years 1 months ago
Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16
Although division is less frequent than addition and multiplication, because of its longer latency it dissipates a substantial part of the energy in floating-point units. In this ...
Alberto Nannarelli, Tomás Lang
TRIDENTCOM
2008
IEEE
15 years 4 months ago
Performance analysis of a lightweight NEMO implementation for low-end devices
IETF Network Mobility (NEMO) Basic Support Protocol is an IP mobility management protocol designed to provide seamless IP mobility to complete networks. This protocol is of crucia...
J. L. Almodovar, Antonio de la Oliva, C. Lazo Ram,...
BMCBI
2007
219views more  BMCBI 2007»
14 years 9 months ago
MetaQTL: a package of new computational methods for the meta-analysis of QTL mapping experiments
Background: Integration of multiple results from Quantitative Trait Loci (QTL) studies is a key point to understand the genetic determinism of complex traits. Up to now many effor...
Jean-Baptiste Veyrieras, Bruno Goffinet, Alain Cha...