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CEC
2007
IEEE
15 years 4 months ago
Target shape design optimization by evolving splines
Abstract— Target shape design optimization problem (TSDOP) is a miniature model for real world design optimization problems. It is proposed as a test bed to design and analyze op...
Pan Zhang, Xin Yao, Lei Jia, Bernhard Sendhoff, Th...
CGO
2007
IEEE
15 years 4 months ago
Microarchitecture Sensitive Empirical Models for Compiler Optimizations
This paper proposes the use of empirical modeling techniques for building microarchitecture sensitive models for compiler optimizations. The models we build relate program perform...
Kapil Vaswani, Matthew J. Thazhuthaveetil, Y. N. S...
CSFW
2007
IEEE
15 years 4 months ago
Secure Implementations for Typed Session Abstractions
mplementations for Typed Session Abstractions Ricardo Corin1,2,3 Pierre-Malo Deni´elou1,2 C´edric Fournet1,2 Karthikeyan Bhargavan1,2 James Leifer1 1 MSR-INRIA Joint Centre 2 Mic...
Ricardo Corin, Pierre-Malo Deniélou, C&eacu...
DDECS
2007
IEEE
175views Hardware» more  DDECS 2007»
15 years 4 months ago
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...
GLVLSI
2007
IEEE
171views VLSI» more  GLVLSI 2007»
15 years 4 months ago
Combinational equivalence checking for threshold logic circuits
Threshold logic is gaining prominence as an alternative to Boolean logic. The main reason for this trend is the availability of devices that implement these circuits efficiently (...
Tejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevo...