Sciweavers

2756 search results - page 446 / 552
» Computation-Centric Memory Models
Sort
View
124
Voted
CF
2007
ACM
15 years 7 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
156
Voted
EH
2004
IEEE
117views Hardware» more  EH 2004»
15 years 7 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
140
Voted
ISHPC
2000
Springer
15 years 7 months ago
Automatic Generation of OpenMP Directives and Its Application to Computational Fluid Dynamics Codes
The shared-memory programming model is a very effective way to achieve parallelism on shared memory parallel computers. As great progress was made in hardware and software technolo...
Haoqiang Jin, Michael A. Frumkin, Jerry C. Yan
107
Voted
RT
2000
Springer
15 years 7 months ago
Hierarchical Instantiation for Radiosity
We present the concept of hierarchical instantiation for radiosity. This new method enables an efficient, yet accurate determination of the illumination in very large scenes, wher...
Cyril Soler, François X. Sillion
153
Voted
PLDI
1995
ACM
15 years 7 months ago
Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
Jack L. Lo, Susan J. Eggers