Sciweavers

2756 search results - page 70 / 552
» Computation-Centric Memory Models
Sort
View
ISCAS
2005
IEEE
97views Hardware» more  ISCAS 2005»
15 years 9 months ago
Two-level decoupled Hamming network for associative memory under noisy environment
— Compared with a single level Hamming associative memory, a simple model based on uniform random noise analysis has proved a twolevel decoupled Hamming network to be an efficie...
Liang Chen, Naoyuki Tokuda, Akira Nagai
ISPASS
2005
IEEE
15 years 9 months ago
Accelerating Multiprocessor Simulation with a Memory Timestamp Record
We introduce a fast and accurate technique for initializing the directory and cache state of a multiprocessor system based on a novel software structure called the memory timestam...
Kenneth C. Barr, Heidi Pan, Michael Zhang, Krste A...
HPCC
2005
Springer
15 years 9 months ago
Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
Francisco J. Villa, Manuel E. Acacio, José ...
161
Voted
ASIASIM
2004
Springer
15 years 9 months ago
LSTAFF: System Software for Large Block Flash Memory
Abstract. Recently, flash memory is widely used in embedded applications since it has strong points: non-volatility, fast access speed, shock resistance, and low power consumption...
Tae-Sun Chung, Dong-Joo Park, Yeonseung Ryu, Sugwo...
FPL
2007
Springer
105views Hardware» more  FPL 2007»
15 years 10 months ago
An Execution Model for Hardware/Software Compilation and its System-Level Realization
We introduce a new execution model for orchestrating the interaction between the conventional processor and the reconfigurable compute unit in adaptive computer systems. We then ...
Holger Lange, Andreas Koch