Sciweavers

1191 search results - page 112 / 239
» Compute the Term Contributed Frequency
Sort
View
DAC
2004
ACM
15 years 11 months ago
A method for correcting the functionality of a wire-pipelined circuit
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
Vidyasagar Nookala, Sachin S. Sapatnekar
DAC
2004
ACM
15 years 11 months ago
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, ...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
DAC
2005
ACM
15 years 11 months ago
Microarchitecture-aware floorplanning using a statistical design of experiments approach
Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi...
Vidyasagar Nookala, Ying Chen, David J. Lilja, Sac...
DAC
2006
ACM
15 years 11 months ago
An adaptive FPGA architecture with process variation compensation and reduced leakage
Process induced threshold voltage variations bring about fluctuations in circuit delay, that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensate...
Georges Nabaa, Navid Azizi, Farid N. Najm
WWW
2006
ACM
15 years 10 months ago
Probabilistic models for discovering e-communities
The increasing amount of communication between individuals in e-formats (e.g. email, Instant messaging and the Web) has motivated computational research in social network analysis...
Ding Zhou, Eren Manavoglu, Jia Li, C. Lee Giles, H...