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VLSID
2009
IEEE
143views VLSI» more  VLSID 2009»
15 years 10 months ago
SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems
Dynamic reconfiguration techniques are widely used for efficient system optimization. Dynamic cache reconfiguration is a promising approach for reducing energy consumption as well...
Weixun Wang, Prabhat Mishra, Ann Gordon-Ross
VLSID
2009
IEEE
139views VLSI» more  VLSID 2009»
15 years 10 months ago
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration
Increasing the number of cores in a multi-core processor reduces per-core performance. On the other hand, providing more resources to each core limits the number of cores on a chi...
Tameesh Suri, Aneesh Aggarwal
VLSID
2009
IEEE
144views VLSI» more  VLSID 2009»
15 years 10 months ago
Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications
The current paradigm of using Cu interconnects for on-chip global communication is rapidly becoming a serious performance bottleneck in ultra-deep submicron (UDSM) technologies. C...
Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi
ICCAD
2004
IEEE
114views Hardware» more  ICCAD 2004»
15 years 6 months ago
Simultaneous short-path and long-path timing optimization for FPGAs
This paper presents the Routing Cost Valleys (RCV) algorithm – the first published algorithm that simultaneously optimizes all short- and long-path timing constraints in a Field...
Ryan Fung, Vaughn Betz, William Chow
HAPTICS
2009
IEEE
15 years 4 months ago
Gait enhancing mobile shoe (GEMS) for rehabilitation
Individuals with certain types of central nervous system damage, such as stroke, have an asymmetric walking gait. Using a splitbelt treadmill, where each leg walks at a different ...
Allison de Groot, Ryan Decker, Kyle B. Reed