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    DAC
    2005
    ACM
    93views Computer Architecture» more  DAC 2005»
    Secure scan: a design-for-test architecture for crypto chips
    16 years 4 months ago
    Secure scan: a design-for-test architecture for crypto chips
    Download  www.inf.ethz.ch
    Bo Yang, Kaijie Wu, Ramesh Karri
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    DAC
    2006
    ACM
    82views Computer Architecture» more  DAC 2006»
    Towards the automatic exploration of arithmetic-circuit architectures
    16 years 4 months ago
    Towards the automatic exploration of arithmetic-circuit architectures
    Download  lap.epfl.ch
    Ajay K. Verma, Paolo Ienne
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    VLSID
    2007
    IEEE
    120views VLSI» more  VLSID 2007»
    VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition
    16 years 3 months ago
    VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition
    Download  www.utdallas.edu
    Chitranjan K. Singh, Sushma Honnavara Prasad, Pora...
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    VLSID
    2006
    IEEE
    111views VLSI» more  VLSID 2006»
    An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip
    16 years 3 months ago
    An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip
    Download  otc.rutgers.edu
    Hari Vijay Venkatanarayanan, Michael L. Bushnell
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    EUROPAR
    2009
    Springer
    144views Distributed And Parallel Com...» more  EUROPAR 2009»
    A Multilevel Parallelization Framework for High-Order Stencil Computations
    15 years 9 months ago
    A Multilevel Parallelization Framework for High-Order Stencil Computations
    Download  cacs.usc.edu
    Stencil based computation on structured grids is a common kernel to broad scientific applications. The order of stencils increases with the required precision, and it is a challeng...
    Hikmet Dursun, Ken-ichi Nomura, Liu Peng, Richard ...
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