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HPCA
2009
IEEE
16 years 6 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
HPCA
2007
IEEE
16 years 6 months ago
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
Ricardo Fernández Pascual, José M. G...
HPCA
2005
IEEE
16 years 6 months ago
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
Simultaneous multithreading (SMT) and chip multiprocessing (CMP) both allow a chip to achieve greater throughput, but their relative energy-efficiency and thermal properties are s...
Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadro...
ECCV
2004
Springer
16 years 8 months ago
A Biologically Motivated and Computationally Tractable Model of Low and Mid-Level Vision Tasks
This paper presents a biologically motivated model for low and mid-level vision tasks and its interpretation in computer vision terms. Initially we briefly present the biologically...
Iasonas Kokkinos, Rachid Deriche, Petros Maragos, ...
IPPS
2007
IEEE
16 years 17 days ago
Predictive Resource Scheduling in Computational Grids
The integration of clusters of computers into computational grids has recently gained the attention of many computational scientists. While considerable progress has been made in ...
Clovis Chapman, Mirco Musolesi, Wolfgang Emmerich,...