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» Computer aided analysis and design of power transformers
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DAC
2007
ACM
16 years 25 days ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid
DAC
2005
ACM
15 years 1 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
ISLPED
2004
ACM
88views Hardware» more  ISLPED 2004»
15 years 5 months ago
Architecting voltage islands in core-based system-on-a-chip designs
Voltage islands enable core-level power optimization for Systemon-Chip (SoC) designs by utilizing a unique supply voltage for each core. Architecting voltage islands involves isla...
Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu ...
DAC
2011
ACM
13 years 11 months ago
Non-uniform micro-channel design for stacked 3D-ICs
Micro-channel cooling shows great potential in removing high density heat in 3D circuits. The current micro-channel heat sink designs spread the entire surface to be cooled with m...
Bing Shi, Ankur Srivastava, Peng Wang
DAC
2006
ACM
16 years 24 days ago
Criticality computation in parameterized statistical timing
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...
Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswa...