Sciweavers

11565 search results - page 100 / 2313
» Computing Minimal Mappings
Sort
View
FPGA
2006
ACM
129views FPGA» more  FPGA 2006»
15 years 7 months ago
Power-aware RAM mapping for FPGA embedded memory blocks
Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a ...
Russell Tessier, Vaughn Betz, David Neto, Thiagara...
133
Voted
CLUSTER
2007
IEEE
15 years 10 months ago
Optimal synchronization frequency for dynamic pipelined computations on heterogeneous systems
— In this paper we give a theoretical model for determining the synchronization frequency that minimizes the parallel execution time of loops with uniform dependencies dynamicall...
Florina M. Ciorba, Ioannis Riakiotakis, Theodore A...
DAC
2001
ACM
16 years 4 months ago
Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-Talk
Yehia Massoud, Jamil Kawa, Don MacMillen, Jacob Wh...
127
Voted
MOBIHOC
2003
ACM
16 years 3 months ago
Minimizing broadcast latency and redundancy in ad hoc networks
Rajiv Gandhi, Srinivasan Parthasarathy 0002, Arune...