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» Computing bounds for fault tolerance using formal techniques
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DSD
2009
IEEE
90views Hardware» more  DSD 2009»
15 years 4 months ago
Instruction Precomputation for Fault Detection
—Fault tolerance (FT) is becoming increasingly important in computing systems. This work proposes and evaluates the instruction precomputation technique to detect hardware faults...
Demid Borodin, Ben H. H. Juurlink, Stefanos Kaxira...
ISCAPDCS
2001
14 years 11 months ago
Tolerating Transient Faults through an Instruction Reissue Mechanism
In this paper, we propose a fault-tolerant mechanism for microprocessors, which detects transient faults and recovers from them. There are two driving force to investigate fault-t...
Toshinori Sato, Itsujiro Arita
DSN
2002
IEEE
15 years 2 months ago
A Portable and Fault-Tolerant Microprocessor Based on the SPARC V8 Architecture
The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32-bit processor based on the SPARC V8 instruction set. The processors toler...
Jiri Gaisler
ICDCSW
2008
IEEE
15 years 4 months ago
Automated Addition of Fault-Tolerance to SCR Toolset: A Case Study
Automated addition of fault-tolerance to existing programs is highly desirable, as it allows the designer to focus on the system behavior in the absence of faults and leave the fa...
Fuad Abujarad, Sandeep S. Kulkarni
SOSP
2007
ACM
15 years 6 months ago
Attested append-only memory: making adversaries stick to their word
Researchers have made great strides in improving the fault tolerance of both centralized and replicated systems against arbitrary (Byzantine) faults. However, there are hard limit...
Byung-Gon Chun, Petros Maniatis, Scott Shenker, Jo...