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CODES
2007
IEEE
15 years 11 months ago
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...
Brett H. Meyer, Donald E. Thomas
ERSA
2009
147views Hardware» more  ERSA 2009»
15 years 2 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias

Source Code
2890views
17 years 17 days ago
ImageJ
"ImageJ can display, edit, analyze, process, save, and print 8-bit, 16-bit and 32-bit images. It can read many image formats including TIFF, PNG, GIF, JPEG, BMP, DICOM, FITS, ...
National Institute of Health
IPPS
2002
IEEE
15 years 9 months ago
System-Level Analysis for MPEG-4 Decoding on a Multi-Processor Architecture
The convergence of TV and new features such as Internet and games, requires a generic media-processing platform, that enables simultaneous execution of very diverse tasks, ranging...
Egbert G. T. Jaspers, Erik B. van der Tol, Peter H...
IPPS
2007
IEEE
15 years 11 months ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao