1474 search results - page 86 / 295 » Computing in Memory Architectures for Digital Image Processi... |
149
click to vote
VLSISP
2011
14 years 11 months ago
2011
Abstract Fractional Motion Estimation (FME) in highdefinition H.264 presents a significant design challenge in terms of memory bandwidth, latency and area cost as there are various...
108
click to vote
IPPS
1996
IEEE
15 years 9 months ago
1996
IEEE
This paper presents the design and implementation of a Sliding Memory Plane (SliM) Array Processor, a mesh-connected SIMD architecture. To build the array processor, we developed ...
158
Voted
ECCV
2008
Springer
16 years 6 months ago
2008
Springer
Abstract. The inhomogeneous Poisson (Laplace) equation with internal Dirichlet boundary conditions has recently appeared in several applications ranging from image segmentation [1,...
125
click to vote
ARVLSI
1999
IEEE
15 years 9 months ago
1999
IEEE
We describe a multi-chip CMOS VLSI visual motion processing system which combines analog circuitry with an asynchronous digital interchip communications protocol to allow more com...
112
click to vote
SIAMMAX
2010
14 years 11 months ago
2010
Computational resolution enhancement (superresolution) is generally regarded as a memory intensive process due to the large matrix-vector calculations involved. In this paper, a de...