Sciweavers

4401 search results - page 836 / 881
» Computing with Default Logic
Sort
View
EMSOFT
2006
Springer
15 years 1 months ago
Modeling a system controller for timing analysis
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...
Stephan Thesing
ALT
1995
Springer
15 years 1 months ago
Learning Unions of Tree Patterns Using Queries
This paper characterizes the polynomial time learnability of TPk, the class of collections of at most k rst-order terms. A collection in TPk de nes the union of the languages de n...
Hiroki Arimura, Hiroki Ishizaka, Takeshi Shinohara
SPIN
2000
Springer
15 years 1 months ago
Verification and Optimization of a PLC Control Schedule
Abstract. We report on the use of model checking techniques for both the verification of a process control program and the derivation of optimal control schedules. Most of this wor...
Ed Brinksma, Angelika Mader
FPGA
1995
ACM
93views FPGA» more  FPGA 1995»
15 years 1 months ago
Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping
In this paper, we present an improvement of the FlowMap algorithm, named CutMap, which combines depth and area minimization in the mapping process by computing min-cost min-height...
Jason Cong, Yean-Yow Hwang
DAC
1994
ACM
15 years 1 months ago
Optimum Functional Decomposition Using Encoding
In this paper, we revisit the classical problem of functional decomposition [1, 2] that arises so often in logic synthesis. One basic problem that has remained largely unaddressed...
Rajeev Murgai, Robert K. Brayton, Alberto L. Sangi...