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DAC
2007
ACM
16 years 6 months ago
Scan Test Planning for Power Reduction
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
DAC
2007
ACM
16 years 6 months ago
An Efficient Mechanism for Performance Optimization of Variable-Latency Designs
In many designs, the worst-case-delay path may never be exercised or may be exercised infrequently. For those designs, a strategy of optimizing a circuit for the worst-case condit...
Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgo...
DAC
2000
ACM
16 years 6 months ago
Self-test methodology for at-speed test of crosstalk in chip interconnects
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...
Xiaoliang Bai, Sujit Dey, Janusz Rajski
DAC
2002
ACM
16 years 6 months ago
Retargetable binary utilities
Since software is playing an increasingly important role in systemon-chip, retargetable compilation has been an active research area in the last few years. However, the retargetti...
Maghsoud Abbaspour, Jianwen Zhu
DAC
2002
ACM
16 years 6 months ago
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...