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98
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ITC
1999
IEEE
105views Hardware» more  ITC 1999»
15 years 4 months ago
Finite state machine synthesis with concurrent error detection
A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
Chaohuang Zeng, Nirmal R. Saxena, Edward J. McClus...
FDTC
2007
Springer
82views Cryptology» more  FDTC 2007»
15 years 6 months ago
Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations
Richard Stern, Nikhil Joshi, Kaijie Wu, Ramesh Kar...
52
Voted
DATE
2006
IEEE
148views Hardware» more  DATE 2006»
15 years 6 months ago
Berger code-based concurrent error detection in asynchronous burst-mode machines
Sobeeh Almukhaizim, Yiorgos Makris