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ATS
2003
IEEE
126views Hardware» more  ATS 2003»
15 years 9 months ago
Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces
Abstract: As a result of variations in the fabrication process, different memory components are produced with different operational characteristics, a situation that complicates th...
Zaid Al-Ars, A. J. van de Goor
ICCD
2003
IEEE
113views Hardware» more  ICCD 2003»
15 years 9 months ago
Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity
As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-o...
Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nour...
MSE
2003
IEEE
101views Hardware» more  MSE 2003»
15 years 9 months ago
Internet-based Tool for System-On-Chip Project Testing and Grading
A tool has been developed to automate the testing and grading of design projects implemented in reprogrammable hardware. The server allows multiple students to test circuits in FP...
Christopher K. Zuver, Christopher E. Neely, John W...
ITC
2000
IEEE
80views Hardware» more  ITC 2000»
15 years 8 months ago
A stand-alone integrated test core for time and frequency domain measurements
An area efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstructi...
Mohamed Hafed, Nazmy Abaskharoun, Gordon W. Robert...
DAC
1996
ACM
15 years 8 months ago
Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths
The testability of basic DSP datapath structures using pseudorandom built-in self-test techniques is examined. The addition of variance mismatched signals is identified as a testi...
Laurence Goodby, Alex Orailoglu