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DAGSTUHL
2006
14 years 11 months ago
Physical 2D Morphware and Power Reduction Methods for Everyone
Dynamic and partial reconfiguration discovers more and more the focus in academic and industrial research. Modern systems in e.g. avionic and automotive applications exploit the p...
Jürgen Becker, Michael Hübner, Katarina ...
DAC
2005
ACM
15 years 10 months ago
Multilevel full-chip routing for the X-based architecture
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-J...
ASPDAC
2006
ACM
120views Hardware» more  ASPDAC 2006»
15 years 3 months ago
A novel framework for multilevel full-chip gridless routing
— Due to its great flexibility, gridless routing is desirable for nanometer circuit designs that use variable wire widths and spacings. Nevertheless, it is much more difficult ...
Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin
DATE
2000
IEEE
142views Hardware» more  DATE 2000»
15 years 1 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
ISCC
2005
IEEE
116views Communications» more  ISCC 2005»
15 years 3 months ago
TPA: A Transport Protocol for Ad Hoc Networks
Several previous works have shown that TCP exhibits poor performance in Mobile Ad Hoc Networks (MANETs). The ultimate reason for this is that MANETs behave in a significantly diff...
Giuseppe Anastasi, Emilio Ancillotti, Marco Conti,...